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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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16K x 64 CAM
The MCM69C433 is a flexible content-addressable memory (CAM) that can contain 16K entries of 64 bits each. The widths of the match field and the output field are programmable, and the match time is designed to be 240 ns. As a result, the MCM69C433 is well suited for datacom applications such as Virtual Path Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C433 is user-defined, with a trade-off between the time between the match request rate and the rate of new entries added to the CAM per second.
MCM69C433 SCM69C433
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* * * * * * * * * * * * *
16K Entries 240 ns Match Time Mask Register to "Don't Care" Selected Bits O Depth Expansion by Cascading Multiple Devices IC M 66 MHz Maximum Clock Rate SE Programmable Match and Output Field Widths E Concurrent Matching of Virtual Path Circuits and Virtual Connection AL Circuits in ATM Mode SC Separate Ports for Control and Match Operations E E 450 ns Insertion Time if 1 of 14 Entry Queue Locations is Empty FR 120 ms Initialization Time After Fast Insertion (at Power-Up Only) BY Single 3.3 V 5% Supply D E IEEE Standard 1149.1 Test Port (JTAG) IV 100-Pin TQFP Package H
, OR T UC ND
C IN
.
TQ PACKAGE TQFP CASE 983A-01
Related Products
C AR
-- MCM69C232, MCM69C432, MCM69C233 (CAMs)
CONTROL PORT
14 x 64 ENTRY QUEUE
MATCH PORT
MQ31 - MQ0 A2 - A0 DQ15 - DQ0 SEL WE IRQ DTACK RESET KMODE INPUT REG STATUS/ CONTROL LOGIC
16K x 64 CAM TABLE
K G LH/SM LL MC MS VPC
REV 3 6/11/01
(c) Motorola, Inc. 2001 MOTOROLA FAST SRAM
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MCM69C433*SCM69C433 1
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PIN ASSIGNMENT
MQ10 MQ11 VSS VDD MQ12 MQ13 MQ14 MQ15 LL VDD VSS LH/SM MQ16 MQ17 MQ18 MQ19 VDD VSS MQ20 MQ21 MQ9 MQ8 VSS VDD MQ7 MQ6 MQ5 MQ4 VSS VDD MQ3 MQ2 MQ1 MQ0 VSS VDD DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 DQ9 DQ8 VDD VSS DQ7 DQ6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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H RC A
D VE I
BY
E RE F
E AL SC
S
O IC EM
, OR T UC ND
MQ22 MQ23 VSS VDD MQ24 MQ25 MQ26 MQ27 VSS VDD MQ28 MQ29 MQ30 MQ31 VSS VDD MC VPC MS G VSS VDD DTACK IRQ RESET TDO VDD VSS TCK TMS
C IN
.
MCM69C433*SCM69C433 2
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DQ5 DQ4 VDD VSS DQ3 DQ2 DQ1 DQ0 K VSS VDD A2 A1 A0 WE SEL KMODE VDD TRST TDI
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PIN DESCRIPTIONS
Pin Locations 42 - 44 58 17 - 20, 23 - 26, 29 - 32, 35 - 38 61 57 39 47 89 92 64 Symbol A2 - A0 DTACK DQ15 - DQ0 G IRQ K KMODE LH/SM LL MC MQ31 - MQ0 Type Input Output I/O Input Output Input Input Input Input 3-bit control port address bus. Control port data transfer acknowledge (Open Drain). 16-bit bidirectional control port data bus. Output Enable control of MQ31 - MQ0. Control port interrupt (Open Drain). Interface Clock, max frequency of 66 MHz. See Note. Description
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67 - 70, 73 - 76, 79 - 82, 85 - 88, 93 - 96, 99, 100, 1, 2, 5 - 8, 11 - 14 62 56 46 52 50 55 51 49 63 45 4, 10, 16, 22, 27, 33, 41, 48, 54, 59, 65, 71, 77, 84, 91, 97 3, 9, 15, 21, 28, 34, 40, 53, 60, 66, 72, 78, 83, 90, 98
MS RESET SEL TCK TDI
H TMS RC A TRST
VPC WE VDD
TDO
D VE Output I
Input Input Output Input
, OR T Output Match Complete (Open Drain). UC D I/O 32-bit common I/O CAM data. N for input of match RAM and data RAM Used O values. IC M SE E Output Match Successful (Open Drain). L Input Resets chip to a known state. CA S Input Control EE port chip select, active low. R Test Clock, part of JTAG interface. Input F BY Input Test Data In, part of JTAG interface.
Latch Low. Latches low order bits if match width is > 32 bits. Test Data Out, part of JTAG interface. Test Mode Select, part of JTAG interface. Tap Reset part of JTAG interface.
Latch High/Start Match. Initiates match sequence on match data present on MQ31 - MQ0.
C IN
.
Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has occurred (Open Drain). Control port Write Enable. Power Supply: 3.3 V 5%.
Supply
VSS
Supply
Ground.
NOTE: Assert KMODE 1 clock cycle after RESET is deasserted.
K
RESET
KMODE
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MCM69C433*SCM69C433 3
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ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Supply Voltage (see Note 2) Voltage Relative to VSS (see Note 2) Output Current per Pin Package Power Dissipation (see Note 3) Temperature Under Bias (see Note 3) Commercial Industrial Operating Temperature Storage Temperature Commercial Industrial Symbol VDD Vin Iout PD Tbias -10 to 85 -40 to 85 TA Tstg 0 to 70 -40 to 85 -55 to 125 C C Value 4.6 -0.5 to VDD + 3 V 20 -- Unit V V mA W C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
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NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability will be dependent upon package characteristics and use environment. See Package Thermal Characteristics.
S LE AND CHARACTERISTICS DC OPERATING CONDITIONS CA (VDD = 3.3 V 5%, TS< 120C, Unless Otherwise Noted) J E RE F RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) BY Symbol Min Parameter ED Power Supply Voltage VDD 3.1 V HI Operating Temperature (Junction) TJ -- RC Input Low Voltage VIL -0.5* A
Input High Voltage
O IC EM
, OR T UC ND
C IN
.
Typ 3.3 -- 0 3
Max 3.5 120 0.8 5.5
Unit V C V V
* VIL (min) = -3.0 V ac (pulse width
v 20 ns).
Parameter
VIH
2.2
DC CHARACTERISTICS AND SUPPLY CURRENTS
Symbol IDDA Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- -- 2.4 Max 300 1 1 0.4 -- Unit mA A A V V
Active Power Supply Current Input Leakage Current (0 V
v Vin v VDD) Output Leakage Current (0 V v Vin v VDD)
Output Low Voltage (IOL = 8 mA) Output High Voltage (IOH = -4 mA)
PACKAGE THERMAL CHARACTERISTICS
Rating Thermal Resistance Junction to Ambient (200 lfpm, 4 Layer Board) (see Note 2) Thermal Resistance Junction to Board (Bottom) (see Note 3) Thermal Resistance Junction to Case (Top) (see Note 4) Symbol RJA RJB RJC Max 36 19 8 Unit C/W C/W C/W
NOTES: 1. RAM junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature, and mounting site thermal impedance. 2. Per SEMI G38-87. 3. Indicates the average thermal impedance between the die and the mounting surface. 4. Indicates the average thermal impedance between the die and the case top surface. Measured via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM69C433*SCM69C433 4
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CAPACITANCE (Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance I/O Capacitance Symbol Cin CI/O Min -- -- Max 5 8 Unit pF pF
JUNCTION TO AMBIENT THERMAL CHARACTERISTICS
Board 1 Layer 1 Layer 4 Layer 4 Layer Air (LFPM) 0 200 0 200 JA (C/W) 43 36 33 29
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, OR T AC OPERATING CONDITIONS AND CHARACTERISTICS UC (VDD = 3.3 V 5%, TJ < 120C, Unless Otherwise Noted) ND OReference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing IC Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted M Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns SE E L CONTROL PORT TIMINGS CA Listed Values are for tKHKH = 15 ns) (Voltages Referenced to VSS = 0 V, Max's are tKHKH Dependent and S EE Parameter Symbol Min Max Unit Notes FR Address Valid to SEL Low tAVSL 0 -- ns BY D DTACK Low to Address Invalid tDTLAX 0 -- ns E IV Data Valid to Select Low tDVSL 0 -- ns H RC DTACK Low to Data Invalid tDTLDX 0 -- ns A
Output Valid to DTACK Low WE Valid to Select Low DTACK Low to WE High WE High to Output Active Select Low to DTACK Low Select High to DTACK High DTACK Low to IRQ Low IRQ Low to IRQ High DTACK Low to Select High DTACK High to Select Low Address Valid to Output Valid Select High to Output High Impedance RESET Low to RESET High tQVDTL tWVSL tDTLWH tWHQX tSLDTL tSHDTH tDTLIL tILIH tDTLSH tDTHSL tAVQV tSHQZ tRLRH 2 0 0 2 10 10 10 20 0 0 -- -- 2 x tKHKH -- -- -- -- -- -- -- -- -- -- 8 8 -- ns ns ns ns ns ns ns ns ns ns ns ns ns 1
C IN
.
NOTE: 1. DTACK is delayed when a write is attempted during certain operations. See Functional Description.
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MCM69C433*SCM69C433 5
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MATCH PORT TIMINGS
(Voltages Referenced to VSS = 0 V, Max's are tKHKH Dependent and Listed Values are for tKHKH = 15 ns) Parameter Clock Cycle Time Clock High Time Clock Low Time LHSM or LL Low to Clock High Clock High to LHSM or LL High MQ Input Data Valid to Clock High Clock High to Match Data Invalid Clock High to MQ Valid Clock High to MC High Symbol tKHKH tKHKL tKLKH tLLKH tKHLH tMQVKH tKHMQX Min 15 6 6 3 1 8 2 Max 250 244 244 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles
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Clock High to MC Low Clock High to MS Low Clock High to MS High Clock High to VPC Low Clock High to VPC High G Low to MQ Active G High to MQ High Impedance LH/SM Low to LH/SM Low
H RC A
D VE I
BY
E RE F
E AL SC
S
O IC EM
N , I-- tKHMQV R TO -- tKHMCH C DU tKHMCL -- N
tKHMSL tKHMSH tKHVPL tKHVPH tGLMQX tGHMQZ tSMSM -- -- -- -- -- -- 22
C.
-- -- 13 10 7 8 5 8 5 3.8 5 --
RL = 50 OUTPUT Z0 = 50 VL = 1.5 V
Figure 1. AC Test Load
3.3 V
RH MCM69C433 OUTPUT PIN FANOUT TO LOAD DEVICES
NOTES: 1. For IRQ, DTACK, MS, MC, and VPC; RH = 200 . 2. If multiple MCM69C433s are used, RH should be placed as close to the load devices as possible.
Figure 2. Pullup for Open Drain Outputs
MCM69C433*SCM69C433 6
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FUNCTIONAL DESCRIPTION
The MCM69C433 is a flexible content-addressable memory (CAM) that can contain 16K entries of 64 bits each. The widths of the match field and the output field are programmable, and the match time is designed to be 240 ns. As a result, the MCM69C433 is well suited for datacom applications such as Virtual Path Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to OC12 (622 Mbps) data rates and Media Access Control (MAC) adPROGRAMMING MODEL dress lookup in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C433 is determined by the user, Three types of registers are accessible through the with a trade-off between the match request rate and the rate MCM69C433's control port: I/O registers, an operation regof entries added to/deleted from the CAM. With the minimum ister, and result/condition code registers. Each register is . required 60 ns of idle time between matches, a typical value 16 bits in length. NC I of 370 insertions or deletions per second can be made. See R, Figure 3 for a graph of the relationship between insertion/ ADDRESS O deletion pairs and match duty cycle. REGISTER NAME OFFSET CT BIT NUMBER In its basic operating mode, the MCM69C433 reads a data 0 U 15 D input word through MQ bus and compares it to all the entries I/O REGISTER 0N 0 O in its CAM table. The MC pin is always asserted after the IC comparisons have been made. If a match is found, the MS I/O REGISTER 1 1 M pin is asserted, and the data associated with the matching SE entry is output on the MQ bus. If no match is found, the MQ 2 E I/O REGISTER 2 bus remains in a high-impedance state to facilitate depth ex- L A C pansion via the cascading of multiple CAMs. I/O REGISTER 3 3 ES Before the basic operating mode can be entered, several E start-up functions must be performed. First, the output width OPERATION REGISTER 4 FR and match width must be designated Y setting the by B global-mask register. Second, a choice must be made FLAG REGISTER 5 D between buffered-entry mode and E fast-entry mode. Next, V the 64-bit match/output data pairs must be loaded into the ERROR CODE REGISTER 6 HI of choice, the table may table. Depending on the entry mode C have to be initialized. Optionally, the "almost full" point may AR INTERRUPT REGISTER 7 be set to provide warning of impending table overflow. The input bits to be compared are defined by the global- FLAG BIT DEFINITIONS mask register. The mask bits that are 0 correspond to the bits that are used in the match operation.Typically, the bits that Bit 0: 1 = At least one interrupt enabled, are used in matching are the high order bits in the 64-bit 0 = No interrupts enabled CAM table entries, and the bits that are used as outputs are Bit 1: 1 = Last control port match successful, the low order bits. While any of the bits can be defined as 0 = Last match unsuccessful match bits, the low order 32 bits of an entry are always driven Bit 2: 1 = Table initialized, 0 = Table not initialized on the MQ bus as output data. Bit 3: 1 = Buffered-entry mode, 0 = Fast-entry mode The choice of entry mode is a trade-off between speed of Bit 4: 1 = Entry queue empty, entry and latency before matching operations can begin. In a 0 = Entry queue not empty typical application, the fast-entry mode will be used to load Bit 5: 1 = Entry queue full, 0 = Entry queue not full the initial values into the CAM table. Subsequently, the Bit 6: 1 = CAM table full, 0 = CAM table not full initialize-table operation, which takes 120 ms, must be Bit 7: 1 = Error condition set, 0 = No error executed to establish the required linkages and relationships Bit 8: 1 = Table almost full, 0 = Table not almost full among the entries. After match operations have begun, the Bit 9: 1 = ATM mode, 0 = Standard mode buffered-entry mode should be used to enter new values Bit 10: 1 = Last operation complete, 0 = Not yet complete dynamically; even one addition in fast-entry mode will disable matching until the table is reinitialized. Table insertions ERROR CODES using the buffered-entry mode and the fast-entry mode actually take the same amount of time unless the entry FFFF No error queue is full. The capacity of the queue is 14 entries. FFFD Invalid instruction After the entry mode choice is made, the table can be FFFC Queue not empty for read loaded. Each 64-bit entry is constructed by writing a 16-bit FFFB Table not initialized value to each of the four I/O registers in the control port of the FFFA Queue not empty for write MCM69C433. The insertion can then be processed. After all FFF9 CAM table full the start-up entries have been loaded into the CAM table, FFF8 Entry queue full the initialization operation is run if required. Normal matching operations can then begin. A delete operation is provided to remove stale data from the CAM table. Several error codes are defined in the details of the instruction set. When an error occurs, its corresponding code is written into the error register and the error bit in the flag register is set. The error bit is cleared and the error register is set to FFFF16 by the next write to the operation register.
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MCM69C433*SCM69C433 7
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INTERRUPT BIT DEFINITIONS Bit 0: Bit 1: Bit 2: Bit 3: Bit 4: Bit 5: Bit 6: Bit 7: 1 = Enable interrupt on insert with full entry queue 1 = Enable interrupt on insert with full table 1 = Enable interrupt on completion of CHECK-FOR-VALUE instruction 1 = Enable interrupt on completion of INITIALIZE-TABLE instruction 1 = Enable interrupt on failed attempt to enter fast-entry mode 1 = Enable interrupt on CAM table reaching almost-full point 1 = Enable interrupt on fast read with non-empty queue 1 = Enable interrupt on illegal instruction INSTRUCTION SET DETAILS The MCM69C433 is prepared for match operations by writing data and instructions via the control port. In the general case, required data is loaded into I/O registers 0 - 3, then an instruction is issued by writing an operation code to the operation register. As a result of running an instruction, the CAM table can be modified, bit(s) can be set in the flag register, error codes can be returned in the error code register, and an interrupt can be generated if enabled. For a particular condition to generate an interrupt, the interrupt register bit specific to that condition must be set. The user should verify that the last operation complete bit (bit 10) of the flag register is set before executing the next instruction, if . the instruction just executed modifies I/O registers. See the NC for any exceptions. I Simultaneous Port Operations section
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Operation INSERT VALUE DELETE VALUE CHECK FOR VALUE INITIALIZE TABLE FAST-ENTRY MODE BUFFERED-ENTRY MODE SET ATM MODE
CH RETURN ENTRYR COUNT A
D VE I
, OR T Table 1. MCM69C433 Operation Summary C U D Description OP Code (Base 16) ON IC Loads a new entry into the CAM table 0000 or 000F M ECAM table Removes an entry fromS the 0001 or 000E LE the control port Runs a match cycle via 0006 CA Prepares CAM table for matching 000B S EE Selects entry mode suited for initial CAM table load 0004 FR entry mode suited for simultaneous loading Selects 0005 BY and matching
Enter mode that provides concurrent VPC/VCC search Determines number of entries in CAM Determines match bits to be checked in a match operation Defines CAM almost-full condition Defines table entry that is output by the fast-read operation Outputs one CAM table entry 0008 0003 0002 or 000D 0007 0009 000A
SET GLOBAL-MASK REGISTER SET ALMOST-FULL POINT SET FAST-READ REGISTER FAST READ
INSERT VALUE This instruction is used to load a new match/output value into the CAM. The contents of I/O registers 0 - 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. If the MCM69C433 is running in the buffered-entry mode, the resulting 64-bit value is written to the first available location in the entry queue, and is immediately available for matching. If a buffered insert-value instruction is attempted when the entry queue is full (indicated by bit 5 of the flag register = 1), no value is written, an error code of FFF816 is returned in the error code register, and the error-condition flag (bit 7) is set in the flag register. An interrupt is generated, if enabled by bit 0 of the interrupt register being set. If the MCM69C433 is running in the fast-entry mode, the concatenated 64-bit value is written directly to the CAM array. If an insert-value instruction is attempted when in fast-entry mode and the table is full, no value is written, an error code of FFF916 is returned in the error code register,
and the error-condition flag (bit 7) is set in the flag register. (The table-full condition is indicated by bit 6 of the flag register being set.) An interrupt is generated, if enabled by bit 1 of the interrupt register being set. Only one entry is allowed for a given match pattern. If an entry is made in the table that duplicates an existing match pattern, it will overwrite the entry already in the CAM table, if the CAM is in buffered-entry mode. The user must ensure that no entries with the same match pattern are inserted in fast-entry mode. DELETE VALUE This instruction is used to remove a match/output value from the CAM. The contents of I/O registers 0 - 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. The bits that have a 0 in the corresponding bit of the global-mask register are used to find a matching entry in the CAM table. If such an entry is found, it is invalidated. Note that any bit that is not a
MCM69C433*SCM69C433 8
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match bit as defined by the mask register is ignored for this operation. The operation of the MCM69C433 guarantees that no more than one matching entry can exist in the table, unless they were accidently loaded using fast-entry mode. This must be avoided by the user, as the results of subsequent matches and deletes will be undefined. Example: I/O Register 0 = I/O Register 1 = I/O Register 2 = I/O Register 3 = Concatenated value = Global-Mask Register = 302016 000016 543A16 FE5516 FE55543A0000302016 C0000000FFFFFFFF16 Of the high-order 32 bits, the rightmost 30 bits are cared by the global-mask register. Therefore, the MCM69C433 will delete an entry, if it exists, which has a value of 3E55543A16 in bits 61 - 32. interrupt is generated if enabled by bit 4 of the interrupt register. If this mode is used to enter data, the initialize-table operation must be executed before matching operations can begin. The entry-mode bit and the table-initialized bit of the flag register are cleared by this operation. BUFFERED-ENTRY MODE This instruction is used to enter the buffered-entry mode. When the MCM69C433 is in this mode, insert-value and delete-value operations utilize the entry queue. This mode can be entered at any time. Table entries are available for match operations immediately, without running the initialize- table operation, if all entries are made . this mode. Note that C in if both the buffered-entry and fast-entry modes have been IN , used to input data, none R the entries are available for of O matching until the initialize-table operation is executed. ConT flicting table and queue values are resolved in favor of the UC latest entry in the queue. For example, if there is an entry in ND the CAM, aO corresponding delete-entry in the queue, and a IC later insert-entry in the queue (all with the same match data), theEM queued insert-entry will return a match value.
CHECK FOR VALUE
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This instruction checks for a matching value in the CAM table via the control port. The contents of I/O registers 0 - 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. The S bits that have a 0 in the corresponding bit of the global-mask LE RETURN ENTRY COUNT A register are used to find a matching entry in the CAM table. If This operation is used to determine the number of valid enSC such an entry is found, the last-match-successful bit of the E tries in the MCM69C433. The value is returned in I/O register flag register is set. In addition, the matching entry is E written to 0, and reflects the sum of the number of valid entries in the FR I/O registers 0 - 3, with bit 15 of register 3 as the most signifiY CAM table and the inserts in the entry queue. cant bit, and bit 0 of register 0 as the least significant bit B If no match is found, the last-match-successful bit is D SET GLOBAL-MASK REGISTER cleared. An interrupt is generatedVE the result, if I regardless ofthe operation enabled by bit 2 of the interrupt register, when H This operation is used to indicate the bits to be used in perhas been completed. The C R operation of the MCM69C433 forming matches. A 1 indicates that a bit should be ignored in A guarantees that no more than one matching entry can exist the match operation, while a 0 indicates that a bit should be in the table. If uninterrupted by match port activity, the check used in the match operation. for value instruction will finish in 16 clock cycles. NOTE: If When this operation is executed, the contents of I/O regisboth the control and matching ports are utilized simultaters 0 - 3 are concatenated, with bit 15 of register 3 as the neously, see the Simultaneous Port Operations section. most significant bit, and bit 0 of register 0 as the least signifiINITIALIZE TABLE If fast-entry mode has been used to load the CAM table, the initialize-table operation must be used to establish the needed relationships and linkages between the entries in the table before matching can proceed. Upon completion, this operation sets the table-initialized bit in the flag register, and generates an interrupt if enabled by bit 3 of the interrupt register. It also sets the buffered-entry mode bit in the flag register. This operation makes the programming model's registers read-only for up to 120 ms after the acknowledgment of the op code write cycle. FAST-ENTRY MODE This instruction is used to enter the fast-entry mode. When the MCM69C433 is in this mode, insert-value operations bypass the entry queue and write new table entries directly to the CAM table. The fast-entry mode can only be entered while the entry queue is empty, as reflected by the queue-empty flag being set (bit 4 of the flag register.) If this operation is attempted while the entry queue is not empty, the value FFFA16 is written to the error code register, the error-condition flag (bit 7) is set in the flag register, and an cant bit. The resulting 64-bit value is written to the global- mask register. This operation should be executed before entering required values into the CAM table. Otherwise, the initialize- table instruction must be executed if the global-mask register is changed after data is loaded into the CAM. SET ALMOST-FULL POINT
This operation is used to define the "almost-full" condition in the CAM table. The 14 low-order bits of I/O register 0 are copied to the almost-full-point register. If an entry is added to the MCM69C433 (via the insert-value operation) that causes the valid-entry count to equal the almost-full point, then bit 8 of the flag register is set, and an interrupt is generated if enabled by bit 5 of the interrupt register. The value of the almost-full register can be changed dynamically during match operations. For example, it could first be set to 8192 to generate an interrupt when the table is half full. When that point is reached, the register could be reprogrammed to 12,288 to provide warning that the table has become three- quarters full. The almost-full interrupt is generated, if enabled, based on the number of entries in the CAM table. Entries in the queue are not included in the count.
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SET FAST-READ REGISTER VALUE This operation defines the table address that is output by the fast-read operation. The least significant 14 bits of I/O register 0 are copied to the fast-read register. The queue must be empty when this instruction is executed. FAST READ Bits 60 - 63 may be used for matching in ATM mode if the application requires extra bits. The use of bits 0 - 31 for matching is not supported in ATM mode.
MATCH DUTY CYCLE
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E simultaneous searching for virtual path circuits (VPCs) and FR virtual connection circuits (VCCs). A VCC is detected when both the virtual path identifier (VPI) and the virtual circuit BY D an entry in the identifier (VCI) of an incoming cellE match V CAM. A VPC match occurs whenIthe VPI of an incoming cell H matches the VPI field of a CAM entry that has all 1s as its RC VCI. A VPC match is signalled by the assertion of the VPC A pin along with the MS pin. At 66 MHz, a match is completed in 240 ns, whether the applied VPI/VCI belongs to a VCC or a VPC. The VCI match field must be defined as bits 32 - 47 of each entry. The VPI match data must occupy bits 48 - 59. The VPI can be limited to bits 48 - 55, if the switch handles only User-Network Interface (UNI) protocols. The mask register should be used to "don't care" any unused bits beyond the VPI field. Entering ATM mode will set bit 9 of the flag register. To load a VPC into the CAM table, the desired VPI value is written (right justified) to I/O register 3, FFFF16 is written to I/O register 2 as the VCI field, the upper half of the desired output word is written to I/O register 1, and the lower half of the desired output word is written to I/O register 0. Then, the "INSERT VALUE" instruction is written to the operation register. When performing a match operation, the VCI must be placed in bits 0 - 15 of the MQ port. The VPI is expected on bits 16 - 27, or bits 16 - 23 in the UNI case. Buffered-entry mode insertions and deletions are modified in the following way when the MCM69C433 is in ATM mode. If you try to add a VCC with the same VPI as an existing VPC, you overwrite the VPC. If you try to delete a VCC when the VCC is not in the table, but a VPC with that VPI is in the table, the VPC will be deleted. The CAM table should never contain, simultaneously, a VCC entry and VPC entry with matching VPIs. Violation of this requirement may lead to unpredictable behavior.
MCM69C433*SCM69C433 10
At 66 MHz, the MCM69C433 completes a match 240 ns, or 16 clock cycles, after assertion of the SM signal. HowThis operation is used to output the contents of one entry ever, if entries need to be added to or deleted from the CAM, in the CAM table. The fast-read register is used to specify idle time is needed between match output and match the appropriate entry, and is then auto-incremented. As a rerequests for control port insertions and deletions. At 66 MHz, sult, successive execution of multiple fast-read operations the match duty cycle should be defined at least at 20 clock will provide access to contiguous entries in the CAM table. cycles (300 ns), leaving 2 clock cycles for insertions/ The CAM entry is copied to I/O registers 0 - 3, with bit 15 deletions. The additional clock cycles are used for holding . of register 3 as the most significant bit, and bit 0 of register 0 the match data on the MQ bus.NC Therefore, every 20 clock I as the least significant bit. cycles, when a match operation and data output are comR, The fast-read instruction can only be executed while the pleted, SM can be asserted. O entry queue is empty, as reflected by the queue-empty flag Entries are stored from least value at the top of the table to CT U being set (bit 4 of the flag register.) If this operation is atthe highest value at the bottom. If an entry with a match data tempted while the entry queue is not empty, the value ND any other entry is continually added or value smaller than O FFFC16 is written to the error code register, the error-condidropped C the table, worst-case scenario occurs causing Ifrom tion flag (bit 7) is set in the flag register, and an interrupt is shifting of all other entries. The idle time, in terms of the numM generated if enabled by bit 7 of the interrupt register. ber cycles, needed to perform a worst-case insertion and/or SE E deletion is given by the formula 32,768 x MDC / (MDC - 18) SET ATM MODE AL cycles, where MDC is the match duty cycles. For example, if SC match requests are occurring every 20 clock cycles: When the MCM69C433 is placed in ATM mode, it provides
E
32,768 x 20 clock cycles = 327,680 clock cycles 20 clock cycles - 18 At 66 MHz (15 ns per cycle) = 0.0049152 sec per insert or deletion. If both insertions and deletions are occurring = 102 insertion/deletion pairs per sec (worst-case). More typical cases consist of insertions occurring at one end of the table and deletions occurring at the other end, or when insertions and/or deletions take place toward the middle of the table. The latter scenario would consist of approximately half the total entries being shifted. The idle time, in terms of the number of cycles, needed to perform a typical insertion and/or deletion is given by the formula 16,384 x MDC / (MDC - 18) cycles, where MDC is the match duty cycles. For example, if match requests are occurring every 20 clock cycles: 16,384 x 20 clock cycles = 163,840 clock cycles 20 clock cycles - 18 At 66 MHz (15 ns per cycle) = 0.0024576 sec per insert or deletion. If both insertions and deletions are occurring = 203 insertion/deletion pairs per sec (typical case). The number of insertion/deletion pairs for both cases are depicted in Figure 3. In general, the time for an insertion or deletion is proportional to its distance from the end of the CAM table. That is, entries with the largest match value take the least time to insert or delete, while entries with the smallest values take the most time. Therefore, the effective rate of
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2,500 INSERTION - DELETION PAIRS / SEC 2,000 1,500 1,000 500 0 20 30 40 50 60 70 80 MATCH DUTY CYCLE AT 66 MHz INPUT CLOCK 90 100 WORST CASE TYPICAL
Figure 3. Connections per Second vs Match Cycle Time
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I and entry queue. The flag register is set to 1C16 (setting the CH and table initialized bits). queue empty, buffered-entry mode, AR The error register is set to FFFF16, indicating no errors. Finally, the almost-full register is set to 3FFF16.
TIMING OVERVIEW
CONTROL PORT The control port of the MCM69C433 is asynchronous. Data transfers, both read and write, are initiated by the assertion of the SEL signal. Address values should be valid and WE should be high, when SEL is asserted to begin a read cycle. All values (address, WE, and SEL) should be held until the MCM69C433 asserts DTACK to signal the end of the read cycle. Address and data values should be valid and WE should be low, when SEL is asserted to begin a write cycle. Address, data, WE, and SEL values should be held until the MCM69C433 asserts DTACK to signal the end of the write cycle. MATCH PORT The MCM69C433's match port is synchronous in operation. When the match width is bits, a match cycle can be initiated by presenting the match data on MQ31 - MQ0 and asserting the LH/SM signal with the appropriate setup time relative to the rising edge of the clock. The assertion of the MC output signifies the completion of the match cycle. If a
insertion and deletion is maximized if the longest-lived entries are placed near the beginning of the table and the shortest-lived entries are placed near the end of the table. For an ATM application, this would correspond to the assignment of small VPI values to permanent virtual circuits and large VPI values to switched virtual circuits. Note that at start-up, when entries are loaded into the then initiated as paragraph. E cycle isalternative timing specified in the previous to describe CAM via the fast-entry mode, the process is dominated by L Two diagrams are presented A the Match Port timing. In the first, LH/SM must meet setup the time it takes to execute the initialization instruction that SC follows. The resulting effective rate of loading the CAM at and hold specs across two consecutive clock cycles, while E start-up is approximately 136,500 entries per second. the MQ bus need only be valid for a single cycle. In the seRE F cond diagram, LH/SM need only be asserted for a single RESET BY clock cycle, while the MQ bus must be held valid with D constant data across two clock cycles. E Asserting RESET removes all entries from the CAM table
R, OMS output is also asserted. If the match has been found,T the match is a virtual path circuit match in ATM mode, the VPC UC D output will be asserted with the MS output. Output data, if any, is enabled by the assertion of the G input. ON If the IC match width is greater than 32 bits, the lower bits are first latched into the MCM69C433 by the LL input. The match EM S
C IN
.
V
SIMULTANEOUS PORT OPERATIONS When the control and match ports are utilized simultaneously, certain procedures must be followed. If a CHECK FOR VALUE command is issued, both the last operation complete bit (bit 10) and the entry queue empty bit (bit 4) in the flag register should be set prior to executing the CHECK FOR VALUE command in order to receive valid results. However, matching on the match port can be done directly after the last operation complete flag is set. The match port has priority over the control port during simultaneous operations. DEPTH EXPANSION Multiple CAMs can be cascaded to increase the depth of the match table. The hardware requirements are very straightforward, as the following pins on each device are simply wired in parallel: A2 - A0, DQ15 - DQ0, WE, IRQ, DTACK, MQ31 - MQ0, K, G, LH/SM, MC, MS, and VPC. Four CAMs can be easily cascaded. Simulations show that eight devices can be cascaded if care is taken to minimize the length of the PC board traces connecting the CAMs. The buffered-entry mode prevents multiple matching entries in a single CAM. The check for value instruction should be used to verify that multiple matching entries will not result from a potential new entry. If a match is found in CAM 1, for example, the new value should be placed in CAM 1, where it will replace the existing entry.
v32
MOTOROLA FAST SRAM
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MCM69C433*SCM69C433 11
Freescale Semiconductor, Inc.
DEPTH EXPANSION EXAMPLE CASCADING FOUR MCM69C433s FOR A 64K WORD TABLE CONTROL PORT
CAM 0 A2 - A0 DQ31 - DQ0 SEL0 WE WE A0 - A2 DQ0 - DQ31 MQ0 - MQ31 K G LM/SM MC IRQ IRQ MS DTACK DTACK VPC MQ31 - MQ0 K G LH/SM MC
MATCH PORT
Freescale Semiconductor, Inc...
CAM 1 A0 - A2 DQ0 - DQ31 SEL1
H RC A
D VE I
BY
E WE RE F
IRQ
E AL SC
O IC MQ0 - MQ31 M SE K
G LM/SM MC MS
I R, O CT U ND
N
C.
MS
VPC
DTACK VPC CAM 2 A0 - A2 DQ0 - DQ31 MQ0 - MQ31 K G LM/SM MC IRQ MS DTACK VPC CAM 3 A0 - A2 DQ0 - DQ31 MQ0 - MQ31 K G LM/SM MC IRQ MS DTACK VPC
SEL2 WE
SEL3 WE
MCM69C433*SCM69C433 12
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MOTOROLA FAST SRAM
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MATCH PORT TIMING (SINGLE CLOCK MODE 32-BIT MATCH) ALTERNATE A
MOTOROLA FAST SRAM
H RC A
0 ns
75 ns
150 ns
225 ns
300 ns
375 ns
D VE I
K 0 10 11 12 13 14 1 2 3 4 5 6 7 8 9 15 16
17
18
19
20
21
22
23
BY
LL
t LLKH
E RE F
LHBSM
tKHLH
tLLKH
tKHLH
G tGLMQX tKHMQX DIN tKHMCH
E AL SC
tMQVKH
tGHMQZ tKHMQV tMQVKH
S
MQ31 - MQ0
DOUT tKHMCL tKHMCH
O IC EM
DIN
MC tKHMSH
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tKHVPH
tKHMSL
tKHMSH
MS
, OR T UC ND
tKHVPL
tKHVPH
C IN
VPC
.
MCM69C433*SCM69C433 13
NOTE: See description of Match Port Timing.
Freescale Semiconductor, Inc...
MATCH PORT TIMING (SINGLE CLOCK MODE 32-BIT MATCH) ALTERNATE B
MCM69C433*SCM69C433 14
H RC A
0 ns
75 ns
150 ns
225 ns
300 ns
375 ns
D VE I
K 0 10 11 12 13 14 1 2 3 4 5 6 7 8 9 15 16
17
18
19
20
21
22
23
BY
LL
t LLKH
E RE F
LHBSM
tKHLH
tLLKH
tKHLH
G tKHMQX tGLMQX DIN tKHMCH
E AL SC
tGHMQZ tKHMQV tMQVKH
S
tMQVKH
MQ31 - MQ0
DOUT tKHMCL tKHMCH
O IC EM
DIN
MC tKHMSH
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tKHVPH
tKHMSL
tKHMSH
MS
, OR T UC ND
tKHVPL
tKHVPH
C IN
VPC
.
MOTOROLA FAST SRAM
NOTE: See description of Match Port Timing.
Freescale Semiconductor, Inc...
MOTOROLA FAST SRAM
H RC A
CONTROL PORT TIMING
t DTLAX
D VE I
A2 - A0 A B t AVSL t SLDTL
BY
t AVSL t DTLSH
E RE F
SEL t DTLDX t AVQV
t DVSL DATA - IN t WVSL t DTLWH
t SHQZ DATA - OUT
E AL SC
DQ15 - DQ0
S
WE t SLDTL t DTLIL t SHDTH
O IC EM
t QVDTL
t SHDTH
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t ILIH
, OR T UC ND
DTACK
IRQ
C IN .
MCM69C433*SCM69C433 15
Freescale Semiconductor, Inc.
JTAG
AC OPERATING CONDITIONS AND CHARACTERISTICS FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TJ < 120C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Termination to 1.5 V
TAP CONTROLLER TIMING
Parameter Cycle Time Clock High Time Clock Low Time Symbol tCK Min 30
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Clock Low to Output Valid Clock Low to Output High-Z Clock Low to Output Active Setup Times:
Hold Times:
BY D NOTES: E 1. TDO will High-Z from a clock low edge depending on the current state of the TAP state machine. IV and SHIFT-DR state of the TAP state machine. H 2. TDO is active only in the SHIFT-IR 3. Transition is measuredRC mV from steady-state voltage. This parameter is sampled and not 100% tested. 500 A
tCKH tCK TCK TEST CLOCK tS TMS TEST MODE SELECT tSD TDI TEST DATA IN tA TDO TEST DATA OUT tHR TRST tSR tCKZ tCKX tHD tH tCKL
E RE F
E AL SC
TMS TDI TRST TMS TDI TRST
S
R, tCKH 12O T tCKL UC12 D5 tA N O tC 0 ICKZ Mt 0 E
CKX tS tSD tSR tH tHD tHR 2 2 2 2 2 10
C IN--
-- -- 9 9 9 --
Max
.
Unit ns ns ns ns ns ns ns
Notes
1 2, 3
--
ns
Figure 4. TAP Controller Timing
MCM69C433*SCM69C433 16
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TEST ACCESS PORT DESCRIPTION
INSTRUCTION SET A 5-pin IEEE Standard 1149.1 Test Port (JTAG) is included on this device. When the TAP (Test Access Port) controller is in the SHIFT-IR state, the instruction register is placed between TDI and TDO. In this state, the desired instruction would be serially loaded through the TDI input. TRST resets the TAP controller to the test-logic reset state. The TAP instruction set for this device are as follows. STANDARD INSTRUCTIONS
Instruction BYPASS SAMPLE/PRELOAD Code (Binary) 1111* 0010 0000 1001 Description Bypass instruction Sample and/or preload instruction Extest instruction High-Z all output pins while bypass register is between TDI and TDO
After one clock cycle of TCK, the TAP controller would then be moved to the SHIFT-DR state where the sampled values would be shifted out of TDO (and new values would be shifted in TDI). These values would normally be compared to expected values to test for board connectivity. CLAMP TAP INSTRUCTION The CLAMP instruction is provided to allow the state of the signals driven from the output pins to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO. The signals driven . from the output pins will not change while the CLAMP NC also be used for this instruction is selected. EXTEST could I purpose, but CLAMP shortens the board scan path by insertR, O ing only the bypass register between TDI and TDO. To use CT CLAMP, the SAMPLE/PRELOAD instruction would be used U first to scan in the values that will be driven on the output pins NDinstruction is active. when the CLAMP O HIGH-Z TAP INSTRUCTION M
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EXTEST HIGHZ
SE HIGH-Z provided to allow all E to Theplaced in instruction isdrive state (high-Z). the outputs L be an inactive During the CLAMP 1100 Clamp output pins while CA HIGH-Z instruction the bypass register is connected bebypass register is between S tween TDI and TDO. TDI and TDO EE R BYPASS TAP INSTRUCTION F * Default state at power-up. Y B The BYPASS instruction is the default instruction loaded at SAMPLE/PRELOAD TAP INSTRUCTION D power up. This instruction will place a single shift register VE between TDI and TDO during the SHIFT-DR state of the The SAMPLE/PRELOAD TAPIinstruction is used to allow TAP controller. This allows the board level scan path to be scanning of the boundary scan register without causing interCH shortened to facilitate testing of other devices in the scan ference to the normal operation of the chip logic. The 62-bit AR path.
boundary scan register contains bits for all device signal and clock pins and associated control signals. This register is accessible when the SAMPLE/PRELOAD TAP instruction is loaded into the TAP instruction register in the SHIFT-IR state. When the TAP controller is then moved to the SHIFT- DR state, the boundary scan register is placed between TDI and TDO. This scan register can then be used prior to the EXTEST instruction to preload the output pins with desired values so that these pins will drive the desired state when the EXTEST instruction is loaded. As data is written into TDI, data also streams out TDO which can be used to pre-sample the inputs and outputs. SAMPLE/PRELOAD would also be used prior to the CLAMP instruction to preload the values on the output pins that will be driven out when the CLAMP instruction is loaded. EXTEST TAP INSTRUCTION The EXTEST instruction is intended to be used in conjunction with the SAMPLE/PRELOAD instruction to assist in testing board level connectivity. Normally, the SAMPLE/ PRELOAD instruction would be used to preload all output pins. The EXTEST instruction would then be loaded. During EXTEST, the boundary scan register is placed between TDI and TDO in the SHIFT-DR state of the TAP controller. Once the EXTEST instruction is loaded, the TAP controller would then be moved to the run-test/idle state. In this state, one cycle of TCK would cause the preloaded data on the output pins to be driven while the values on the input pins would be sampled. Note the TCK, not the clock pin (CLK), is used as the clock input while CLK is only sampled during EXTEST. BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input, output, and I/O connections on the device (not counting the TAP pins). The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAM I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary scan register. The Bit Scan Order table (Table 2) describes which device pin connects to each boundary scan register location. The first column defines the bit's position in the boundary scan register. The shift register bit at G (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the pin, third column is the pin number and the fourth column is the pin type (input, output, or I/O). DISABLING THE TEST ACCESS PORT AND BOUNDARY SCAN It is possible to use this device without utilizing the four pins used for the test access port. To circuit disable the device, TCK must be tied to V SS to preclude mid-level inputs. Although TDI and TMS are designed in such a way that an undriven input will produce a response equivalent to the application of a logic 1, it is still advisable to tie these inputs to VDD through a 1K resistor. TDO should remain unconnected.
IC
MOTOROLA FAST SRAM
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Freescale Semiconductor, Inc.
Table 2. Sample/Preload Boundary Scan Register Bit Definitions
Bit No. 1 2 3 4 5 6 7 8 9 10 Bit Pin Name G MS VPC MC MQ31 MQ30 MQ29 MQ28 MQ27 MQ26 MQ25 MQ24 MQ23 MQ22 MQ21 MQ20 MQ19 Bit Pin No. 61 62 63 64 67 68 69 70 73 74 75 76 79 80 Bit No. 33 34 35 36 37 38 39 Bit Pin Name MQ5 MQ4 MQ3 MQ2 MQ1 MQ0 DQ15 Bit Pin No. 7 8 11 12 13 14
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11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
H RC A MQ16
MQ17 LH/SM LL MQ15 MQ14 MQ13 MQ12 MQ11 MQ10 MQ9 MQ8 MQ7 MQ6
MQ18
D VE I
E RE 82 F Y B 85
81 86 87 88 89 92 93 94 95 96 99 100 1 2 5 6
E AL SC
S
NC 40 DQ14 I , OR 41 DQ13 T UC DQ12 42 D 43 DQ11 ON IC DQ10 EM 44
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 K A2 A1 A0 WE SEL RESET IRQ DTACK
.
17 18 19 20 23 24 25 26 29 30 31 32 35 36 37 38 39 42 43 44 45 46 56 57 58
MCM69C433*SCM69C433 18
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TEST ACCESS PORT PINS
TCK -- TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS -- TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic 1 input level. TDI -- TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (see Figure 5). An undriven TDI pin will produce the same result as a logic 1 input level. TDO -- TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (see Figure 5). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST -- TAP RESET This device has a TRST pin. TRST is optional in IEEE 1149.1. Asserting the asynchronous . C TRST places the TAP controller in test-logic reset state. Test-logic reset state can IN also be entered by holding R, high for five rising edges of TMS TCK. This type of reset does not affect the operation of the TO system logic. UC
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1
TEST-LOGIC RESET 0
0
RUN-TEST/ IDLE
1
H RC A
D VE I
BY
E RE DR-SCAN F SELECT
0 1 CAPTURE-DR
E AL SC
S
ON IC M E
D
SELECT IR-SCAN 1 0 1
1
CAPTURE-IR
0 SHIFT-DR 0
0 SHIFT-IR 0
1 EXIT1-DR 0 PAUSE 1-DR 0 1
1 EXIT1-IR 0 PAUSE-IR 0 1
1 0 EXIT2-DR 1 PAUSE 2-DR 1 0 1 0
1 EXIT2-IR 1 UPDATE-IR 0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
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ORDERING INFORMATION
(Order by Full Part Number) MCM SCM
Motorola Memory Prefix MCM = Commercial Temp. SCM = Industrial Temp. Part Number Full Commercial Part Numbers -- MCM69C433TQ15 Full Industrial Part Numbers -- SCM69C433TQ15
69C433
XX
XX X
Blank = Trays, R = Tape and Reel Speed (15 = 15 ns) Package (TQ = TQFP) MCM69C433TQ15R SCM69C433TQ15R
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H RC A
D VE I
BY
E RE F
E AL SC
S
O IC EM
, OR T UC ND
C IN
.
MCM69C433*SCM69C433 20
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PACKAGE DIMENSIONS
TQ PACKAGE TQFP CASE 983A-01
4X
e 0.20 (0.008) H A-B D
2X 30 TIPS
0.20 (0.008) C A-B D -D-
80 81 51 50
e/2
B E/2 B VIEW Y E1 E E1/2 -X-
-A-
-B-
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100 1 30
31
c
D1/2 D1 D
2X 20 TIPS
D/2
0.20 (0.008) C A-B D
A -H- -C-
SEATING PLANE
H RC A
S
D VE I
BY
E RE F
q2
E AL SC
S
0.13 (0.005)
0.10 (0.004) C
q3
VIEW AB
0.05 (0.002)
S
q1
0.25 (0.010) A2 R2
GAGE PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 3. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
A1
R1
L2 L L1 VIEW AB
q
MOTOROLA FAST SRAM
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EEEE CCCC EEEE CCCC
b
M
O IC EM
, OR T UC ND
BASE METAL
C IN
.
X=A, B, OR D
PLATING
b1 c1
C A-B
S
D
S
SECTION B-B
q q1 q2 q3
MCM69C433*SCM69C433 21
Freescale Semiconductor, Inc.
NOTES
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H RC A
D VE I
BY
E RE F
E AL SC
S
O IC EM
, OR T UC ND
C IN
.
MCM69C433*SCM69C433 22
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MOTOROLA FAST SRAM
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NOTES
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H RC A
D VE I
BY
E RE F
E AL SC
S
O IC EM
, OR T UC ND
C IN
.
MOTOROLA FAST SRAM
For More Information On This Product, Go to: www.freescale.com
MCM69C433*SCM69C433 23
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
H RC A
D VE I
BY
E RE F
E AL SC
S
O IC EM
, OR T UC ND
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE : http://motorola.com/semiconductors /
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334
MCM69C433*SCM69C433 24
For More Information On This Product, Go to: www.freescale.com
MCM69C433/D MOTOROLA FAST SRAM

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